Cypress Semiconductor /psoc63 /SRSS /CLK_FLL_CONFIG3

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Interpret as CLK_FLL_CONFIG3

BYPASS_SEL=AUTO

Description

FLL Configuration Register 3

Fields

FLL_LF_IGAIN	FLL Loop Filter Integral Gain Setting 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 =12: illegal
FLL_LF_PGAIN	FLL Loop Filter Proportional Gain Setting 0: 1/256 1: 1/128 2: 1/64 3: 1/32 4: 1/16 5: 1/8 6: 1/4 7: 1/2 8: 1.0 9: 2.0 10: 4.0 11: 8.0 =12: illegal
SETTLING_COUNT	Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts. A delay allows the CCO output to settle and gives a more accurate measurement. The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case. 0: no settling time 1: wait one reference clock cycle … 8191: wait 8191 reference clock cycles
BYPASS_SEL	Bypass mux located just after FLL output. 0 (AUTO): Automatic using lock indicator. When unlocked, automatically selects FLL reference input (bypass mode). When locked, automatically selects FLL output. 1 (AUTO1): Same as AUTO 2 (FLL_REF): Select FLL reference input (bypass mode). Ignores lock indicator 3 (FLL_OUT): Select FLL output. Ignores lock indicator.

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